- Our paper titled “NPUWattch: ML-based Power, Area, and Timing Modeling for Neural Accelerators” is accepted by the IEEE International Symposium on High-Performance Computer Architecture (HPCA) 2026. Congrats, Sehyeon, Minkwan, and Chanho! Many thanks to Prof. Taigon Song and his team for years of collaboration.
- Youngin has successfuly defended his Ph.D. thesis. Congratulations, Dr. Kim!
- Our paper titled “Graphite: Hardware-Aware GNN Reshaping for Acceleration with GPU Tensor Cores” is accepted by the IEEE Transactions on Parallel and Distributed Systems (TPDS). Kudos to Hyeonjin and Taesoo!
- We are excited to celebrate the first PhD graduates from our lab. Congratulations to Dr. Hyeonjin Kim and Dr. Bogil Kim! We wish you all the best in your future endeavors.
- Our paper titled “RoTA: Rotational Torus Accelerator for Wear Leveling of Neural Processing Elements” is accepted by the Design, Automation and Test in Europe Conference and Exhibition (DATE) 2025. Congrats, Taesoo, Hyeonjin, Jingu, and Bogil!
- Our paper titled “Genie Cache: Non-blocking Miss Handling and Replacement in Page-Table-based DRAM Cache” is accepted by the IEEE/ACM International Symposium on Microarchitecture (MICRO) 2024. Congrats, Youngin!
- Our paper titled “Nona: Accurate Power Prediction Model Using Neural Networks” is accepted by the ACM/IEEE Design Automation Conference (DAC) 2024. Congrats, HoSun, Chanho, and Euijun!
- William receives a Teaching Excellence Award from the College of Engineering, Yonsei University, in Apr. 2024.
- Our paper titled “NeuroSpector: Systematic Optimization of Dataflow Scheduling in DNN Accelerators” is accepted by the IEEE Transactions on Parallel and Distributed Systems (TPDS). Well done, Chanho, Bogil, and Sungmin!
- Our paper titled “LAS: Locality-Aware Scheduling for GEMM-Accelerated Convolutions in GPUs” is accepted by the IEEE Transactions on Parallel and Distributed Systems (TPDS). Congrats, Hyeonjin!
- Our paper titled “NOMAD: Enabling Non-blocking OS-managed DRAM Cache via Tag-Data Decoupling” is accepted by the IEEE International Symposium on High-Performance Computer Architecture (HPCA) 2023. Congrats, Youngin and Hyeonjin!
- A paper titled “SnakeByte: A TLB Design with Adaptive and Recursive Page Merging in GPUs” is accepted by the IEEE International Symposium on Computer Architecture (HPCA) 2023. Kudos to all authors!
- William receives a Teaching Excellence Award from the College of Engineering, Yonsei University, in Apr. 2022.
- Memory systems
- Processing in/near memory
- GPU microarchitecture
- Neural accelerators
- ML for systems: power and reliability management
The following courses are relevant to our research interests. Students seeking lab opportunities are strongly encouraged to take these courses. While it is not necessary to take all of them, applicants should have completed at least two of the three bold-faced courses. Strong programming skills are mandatory, e.g., C++, Python, and Verilog. Competitive applicants are expected to have a minimum GPA of 3.5/4.3 (or 4.0/4.5 for students not from Yonsei undergrad). Otherwise, applicants must provide equivalent competence.
- EEE3530 Computer Architecture
- EEE3535 Operating Systems
- EEE3314 Artificial Intelligence
- EEE3540 Microprocessors
- EEE3544 System IC Design
- EEE5501 Advanced Programming
- EEE6504 Compilers
- EEE6510 Advanced Computer Architecture
Eligibility: Applicants interested in joining the lab must have legal residence in South Korea prior to contacting the lab. Please, do not send us emails if you are not legally present in South Korea.
Contact: William J. Song (Office: Engineering Hall #3, C410, Email: wjhsong {\at} yonsei {\dot} ac {\dot} kr, Phone: 2123-2864)